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  HT46R92 a/d type 8-bit mcu with 16  16 high current led driver rev. 1.10 1 november 5, 2008 general description the HT46R92 is an 8-bit high performance risc archi - tecture microcontroller, the device is designed espe - cially for applications that interface directly to analog signals, such as those from sensors. the devices in - clude an integrated multi-channel analog to digital con - verter in addition to two pulse width modulation outputs. an internal high current led driver circuit also provides for easy interfacing to applications which con - tain led displays. the usual holtek mcu features such as power down and wake-up functions, oscillator options, etc. combine to ensure user applications require a minimum of exter - nal components. the benefits of integrated a/d and pwm functions, in addition to low power consumption, high performance, i/o flexibility and low-cost, provides the device with the versatility to suit a wide range of application possibilities such as sensor signal processing, motor driving, indus - trial control, consumer products, subsystem controllers, etc. as is the case with all holtek microcontroller devices, the HT46R92 is fully supported by a full suite of professional hardware and software tools, containing comprehensive features to ensure user applications are designed and debugged in as short a time as possible. features  operating voltage: f sys =32768hz: 2.2v~5.5v f sys =4mhz: 2.2v~5.5v f sys =8mhz: 3.3v~5.5v  8 bidirectional i/o lines  max. 16  16 led driver output  8 led shared i/o lines  24 led shared output  external dual edge triggered interrupt input shared with i/o line  single 8-bit programmable timer/event counters with overflow interrupt  rc/xtal and 32768hz crystal oscillators  dual clock system offers three operating modes  normal mode: both rc/xtal and 32768hz clock active  slow mode: 32768hz clock only  power-down mode can have periodical wake-up using the watchdog timer overflow  watchdog timer  2048  14 program memory  88  8 data memory  power down and wake-up functions to reduce power consumption  up to 0.5  s instruction cycle with 8mhz system clock at v dd =5v  6-level subroutine nesting  6 channel 12-bit resolution a/d converter  2 channel 8-bit pwm output shared with i/o lines  1 / 2 bias 4 common lcd  bit manipulation instruction  table read instructions  63 powerful instructions  all instructions executed in one or two machine cycles  low voltage reset function  44/52-pin qfp package technical document  tools information  faqs  application note  ha0003e communicating between the ht48 & ht46 series mcus and the ht93lc46 eeprom  ha0049e read and write control of the ht1380  ha0075e mcu reset and oscillator circuits application note
block diagram pin assignment HT46R92 rev. 1.10 2 november 5, 2008          
       
            
     
              
    

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pin description pin name i/o configuration option description pa0/bz pa1/bz pa2/tmr pa3 pa4/pwm0 pa5/pwm1 pa6, pa7 i/o pull-high, wake-up, bz/bz , pwm0~pwm1 bidirectional 8-bit input/output port. each individual pin on this port can be config - ured as a wake-up input by a configuration option. software instructions deter - mine if the pin is a cmos output or schmitt trigger input. a configuration option determines if all pins on the port have pull-high resistors. pins pa0, pa1, pa2, pa4 and pa5 are pin-shared with bz, bz , tmr, pwm0 and pwm1, respectively. pb0/an0 pb1/an1 pb2/an2 pb3/an3 pb4/an4 pb5/an5 pb6, pb7 i/o  bidirectional 8-bit input/output port. software instructions determine if the pin is a cmos output or schmitt trigger input. pb is pin-shared with the a/d input pins. the a/d inputs are selected via software instructions. once selected as an a/d in - put, the i/o function is disabled automatically. pc0~pc3 pc4/com0 pc5/com1 pc6/com2 pc7/com3 o  8-bit cmos output port. pc4~pc7 can be used as com0~com3. pd0/int pd1~pd7 i/o o  8-bit cmos output port. pd0 is pin-shared with the external interrupt input pin. pe0~pe7 o  8-bit cmos output port. osc1 osc2 i o crystal or rc osc1, osc2 are connected to an external rc network or external crystal, deter- mined by configuration option, for the internal system clock. if the rc system clock option is selected, pin osc2 can be used to measure the system clock at 1/4 frequency. osc3 osc4 i o  osc3 and osc4 are connected to an external 32768hz crystal oscillator to im- plement a system clock and real time clock. res i  schmitt trigger reset input. active low. vdd  positive power supply vss  negative power supply, ground vref a/d reference voltage input pin. vddb vddc  pb & pc port positive power supply vssd, vsse  pd & pe port negative power supply, ground note: 1. each pin on pa can be programmed through a configuration option to have a wake-up function. 2. as the table applies to the larger package size not all pins may exist on the smaller packages. HT46R92 rev. 1.10 3 november 5, 2008
absolute maximum ratings supply voltage ...........................v ss  0.3v to v ss +6.0v storage temperature ............................  50  cto125  c input voltage..............................v ss  0.3v to v dd +0.3v operating temperature...........................  40  cto85  c i ol total ..............................................................150ma i oh total............................................................  100ma total power dissipation .....................................500mw note: these are stress ratings only. stresses exceeding the range specified under  absolute maximum ratings  may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics ta=25  c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage  f sys =32768hz 2.2  5.5 v  f sys =4mhz 2.2  5.5  f sys =8mhz 3.3  5.5 v v avdd analog operating voltage  v avdd =v dd 2.7  5.5 v i dd1 operating current (crystal osc, rc osc) 3v no load, f sys =4mhz, adc disable  12ma 5v  2.5 5 ma i dd2 operating current (rc osc, rtc osc) 5v no load, f sys =8mhz, adc disable  48ma i dd3 operating current (rtc* osc, rc off) 3v no load, f sys =32768hz, adc disable  20 40  a 5v  50 100  a i stb1 standby current (wdt & rtc* enabled) 3v no load, system halt  35  a 5v  10  a i stb2 standby current (wdt disabled, rtc* enabled) 3v no load, system halt  12  a 5v  24  a i stb3 standby current (wdt enabled & rtc* disabled) 3v no load, system halt  24  a 5v  48  a i stb4 standby current (wdt & rtc* disabled) 3v no load, system halt  1  a 5v  2  a i stb5 standby current with 200k (see note 2) resistor on for 1 / 2 vdd bias (wdt & rtc disabled) 3v no load, system halt  30 50  a v il1 input low voltage for i/o ports  0  0.3v dd v v ih1 input high voltage for i/o ports  0.7v dd  v dd v v il2 input low voltage (res )  0  0.4v dd v v ih2 input high voltage (res )  0.9v dd  v dd v v lvr low voltage reset  1.98 2.1 2.22 v 2.98 3.15 3.32 v 3.98 4.2 4.42 v i ol1 i/o port sink current for pa 3v v ol =0.1v dd 48  ma 5v v ol =0.1v dd 10 20  ma HT46R92 rev. 1.10 4 november 5, 2008
symbol parameter test conditions min. typ. max. unit v dd conditions i ol2 i/o port sink current for pb, pc 3v v ol =0.1v dd 0.6 1.3  ma 5v v ol =0.1v dd 1.5 3.0  ma i ol3 i/o port sink current for pd, pe 3v v ol =0.1v dd 12 24  ma 5v v ol =0.1v dd 30 60  ma i oh1 i/o port source current for pa 3v v oh =0.9v dd  2  4  ma 5v v oh =0.9v dd  5  10  ma i oh2 i/o port source current for pb, pc 3v v oh =0.9v dd  4  8  ma 5v v oh =0.9v dd  10  20  ma i oh3 i/o port source current for pd, pe 3v v oh =0.9v dd 0.25 0.5  ma 5v v oh =0.9v dd 0.5 1.0  ma r ph pull-high resistance 3v  20 60 100 k 5v  10 30 50 k v bias 0.5v dd bias voltage (see note 3) 5v 2.3 2.5 2.7 v v ad a/d input voltage  0  v ref v v ref a/d input reference voltage range  v avdd =2.7v~5.5v 1.6  v avdd + 0.1 v dnl a/d differential non-linearity  v avdd =5v, v ref =v avdd , t ad =0.5  s  2  2 lsb inl a/d integral non-linearity  4  4 lsb i adc additional power consumption if a/d converter is used 3v   0.5 1.0 ma 5v  1.5 3.0 ma note: 1. * rtc osc in slow mode for test condition. 2. set  lcden  =1, set  com0en  =1, reset  rsel  =0 in lcdc (1fh) register for i stb5 measurement. 3. v bias voltage is design guarantee. not for test. 4. v avdd is the analog circuit supply voltage which does not have an external pin but is connected to v dd inside the device. HT46R92 rev. 1.10 5 november 5, 2008
a.c. characteristics ta=25  c symbol parameter test conditions min. typ. max. unit v dd conditions f sys1 system clock (rc osc)  2.2v~5.5v 400  4000 khz  3.3v~5.5v 400  8000 khz f sys2 system clock (rtc osc)  2.2v~5.5v  32768  khz f timer timer i/p frequency (tmr)  2.2v~5.5v 0  4000 khz  3.3v~5.5v 0  8000 khz t wdtosc watchdog oscillator period 3v  45 90 180  s 5v  32 65 130  s f fsp1 f sp time-out period clock source form wdt 3v with prescaler (f s /4096) 184 369 737 ms 5v 131 266 532 ms t fsp2 f sp time-out period clock source form rtc  with prescaler (f s /4096)  125  ms t res external reset low pulse width  1  s t sst system start-up timer period  wake-up from halt  1024  *t sys t lvr low voltage reset time  0.25 1 2 ms t int interrupt pulse width  1  s t ad a/d clock period  0.5  s t adc a/d conversion time   16  t ad note: *t sys =1/f sys1 or 1/f sys2 HT46R92 rev. 1.10 6 november 5, 2008
HT46R92 rev. 1.10 7 november 5, 2008 system architecture a key factor in the high-performance features of the holtek microcontrollers is attributed to the internal sys - tem architecture. the range of devices take advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction exe - cution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all operations of the instruction set. it carries out arith - metic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accumula - tor and the alu. certain internal registers are imple - mented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural fea - tures ensure that a minimum of external components is required to provide a functional i/o and a/d control sys - tem with maximum reliability and flexibility. clocking and pipelining the main system clock, derived from either a crys - tal/resonator or rc oscillator is subdivided into four in- ternally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive in - struction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. when the rc oscillator is used, osc2 is freed for use as a t1 phase clock synchronising pin. this t1 phase clock has a frequency of f sys /4 with a 1:3 high/low duty cycle. for instructions involving branches, such as jump or call instructions, two machine cycles are required to com - plete instruction execution. an extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as  jmp  or  call  that demand a jump to a non-consecutive program memory address. however, it must be noted that only the lower 8 bits, known as the program counter low register, are directly address- able by user. 6 
  
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HT46R92 rev. 1.10 8 november 5, 2008 when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for condi - tional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is dis - carded and a dummy cycle takes its place while the cor - rect instruction is obtained. the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and can be read nor written to. by trans - ferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. the lower byte of the program counter is fully accessi - ble under program control. manipulating the pcl might cause program branching, so an extra cycle is needed to pre-fetch. further information on the pcl register can be found in the special function register section. stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is organised into 8 levels and is neither part of the data nor part of the program space, and is neither be read nor written to. the activated level is indexed by the stack pointer, sp, and can neither be read nor written to. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt rou - tine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the ac - knowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overflow al - lowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine in - struction can still be executed which will result in a stack overflow. precautions should be taken to avoid such cases which might cause unpredictable program branching. mode program counter bits b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 initial reset 0 0000000000 external interrupt 0 0000000100 timer/event counter overflow 0 0000001000 time base interrupt 0 0000001100 a/d converter interrupt 0 0000010000 skip program counter + 2 loading pcl pc10 pc9 pc8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: pc10~pc8: current program counter bits @7~@0: pcl bits #10~#0: instruction code address bits s10~s0: stack register bits the program counter is 11 bits wide, i.e. from b10~b0. )         
  
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HT46R92 rev. 1.10 9 november 5, 2008 arithmetic and logic unit  alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic op - erations of the instruction set. connected to the main microcontroller data bus, the alu receives related in - struction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. as these alu calculation or oper - ations may result in carry, borrow or other status changes, the status register will be correspondingly up - dated to reflect these changes. the alu supports the following functions:  arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa  logic operations: and, or, xor, andm, orm, xorm, cpl, cpla  rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc  increment and decrement inca, inc, deca, dec  branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti program memory the program memory is the location where the user code or program is stored. for this device, the type of memory is one-time programmable, otp, memory where users can program their application code into the device. by us- ing the appropriate programming tools, otp devices of- fer users the flexibility to freely develop their applications which may be useful during debug or for products requir- ing frequent upgrades or program changes. otp devices are also applicable for use in applications that require low or medium volume production runs. structure the program memory has a capacity of 2k by 14 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. table data, which can be setup in any location within the program memory, is addressed by separate table pointer registers. special vectors within the program memory, certain locations are re - served for special usage such as reset and interrupts.  location 000h this vector is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution.  location 004h this vector is used by the external interrupt. if the ex - ternal interrupt pin on the device receives a rising or falling transition, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full.  location 008h this internal vector is used by the timer/event coun - ter 0. if a counter overflow occurs, the program will jump to this location and begin execution if the timer/event counter interrupt is enabled and the stack is not full.  location 00ch this internal vector is used by the time base interrupt. if a time base interrupt occurs, the program will jump to this location and begin execution if the time base in - terrupt is enabled and the stack is not full.  location 010h this internal vector is used by the a/d converter. when an a/d conversion cycle is complete, the pro - gram will jump to this location and begin execution if the a/d interrupt is enabled and the stack is not full. look-up table any location within the program memory can be defined as a look-up table where programmers can store fixed data. to use the look-up table, the table pointer must first be setup by placing the lower order address of the look up data to be retrieved in the table pointer register, tblp. this register defines the lower 8-bit address of the look-up table. after setting up the table pointer, the table data can be retrieved from the current program memory page or last program memory page using the  tabrdc[m]  or  tabrdl [m]  instructions, respectively. when these in - structions are executed, the lower order table byte from the program memory will be transferred to the user de - fined data memory register [m] as specified in the in - struction. the higher order table data byte from the program memory will be transferred to the tblh special register. any unused bits in this transferred higher order byte will be read as  0  . . 6 6 0 2 3   
  
   
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HT46R92 rev. 1.10 10 november 5, 2008 the accompanying diagram illustrates the address - ing/data flow of the look-up table: table program example the following example shows how the table pointer and table data is defined and retrieved from the microcontroller. this example uses raw table data lo - cated in the last page which is stored there using the org statement. the value at this org statement is  700h  which refers to the start address of the last page within the 2k program memory. the table pointer is setup here to have an initial value of  06h  . this will ensure that the first data read from the data table will be at the pro - gram memory address  706h  or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the first address of the present page if the  tabrdc [m]  instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the  tabrdl [m]  instruction is executed. )            #  '  )  '  0  !   c     #  a  b       

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 tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise table pointer - note that this address ; is referenced mov tblp,a ; to the last page or present page : : tabrdl tempreg1 ; transfers value in table referenced by table pointer ; to tempregl ; data at prog. memory address  706h  transferred to ; tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer ; to tempreg2 ; data at prog.memory address  705h  transferred to ; tempreg2 and tblh ; in this example the data  1ah  is transferred to ; tempreg1 and data  0fh  to register tempreg2 ; the value  00h  will be transferred to the high byte ; register tblh : : org 700h ; sets initial address of last page dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : : instruction table location bits b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tabrdc [m] pc10 pc9 pc8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 table location note: pc10~pc8: current program counter bits @7~@0: table pointer tblp bits the table address location is 11 bits, i.e. from b10~b0.
HT46R92 rev. 1.10 11 november 5, 2008 because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the inter - rupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary in - formation is stored. divided into two sections, the first of these is an area of ram where special function registers are located. these registers have fixed locations and are necessary for correct operation of the device. many of these registers can be read from and written to di - rectly under program control, however, some remain protected from user manipulation. the second area of data memory is reserved for general purpose use. all locations within this area are read and write accessible under program control. structure the two sections of data memory, the special purpose and general purpose data memory are located at con - secutive locations. all are implemented in ram and are 8 bits wide but the length of each memory section is dic - tated by the type of microcontroller chosen. the start address of the data memory for all devices is the ad - dress  00h  . registers which are common to all microcontrollers, such as acc, pcl, etc., have the same data memory address. general purpose data memory all programs require an area of read/write memory where temporary data can be stored and retrieved for use later. it is this area of ram memory that is known as general purpose data memory. this area of data mem - ory is fully accessible by the user program for both read and write operations. by using the  set [m].i  and  clr [m].i  instructions individual bits can be set or reset un - der program control giving the user a large range of flex - ibility for bit manipulation in the data memory. +      )   !    
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HT46R92 rev. 1.10 12 november 5, 2008 special purpose data memory this area of data memory is where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant spe - cial function register section. note that for locations that are unused, any read instruction to these addresses will return the value  00h  . special function registers to ensure successful operation of the microcontroller, certain internal registers are implemented in the data memory area. these registers ensure correct operation of internal functions such as timers, interrupts, etc., as well as external functions such as i/o data control and a/d converter operation. the location of these registers within the data memory begins at the address 00h. any unused data memory locations between these special function registers and the point where the general pur - pose memory begins is reserved for future expansion purposes, attempting to read data from these locations will return a value of 00h. indirect addressing registers  iar0, iar1 the iar0 and iar1 registers, located at data memory addresses 00h and 02h, are not physically imple - mented. these special function registers allows what is known as indirect addressing, which permits data ma - nipulation using memory pointers instead of the usual direct memory addressing method where the actual memory address is defined. any actions on the iar0 and iar1 registers will result in corresponding read/write operations to the memory locations specified by the memory pointers mp0 and mp1. reading the iar0 and iar1 registers indirectly will return a result of  00h  and writing to the register indirectly will result in no operation. memory pointer  mp0, mp1 two memory pointers, known as mp0 and mp1, are physically implemented in data memory. the memory pointer can be written to and manipulated in the same way as normal registers providing an easy way of ad - dressing and tracking data. when using any operation on the indirect addressing register iar0 or iar1, it is ac - tually the address specified by the memory pointer that the microcontroller will be directed to. the following example shows how to clear a section of four ram locations already defined as locations adres1 to adres4. data .section
data
adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0
code
org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; accumulator loaded with first ram address mov mp0,a ; setup memory pointer with first ram address loop: clr iar0 ; clear the data at address defined by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specific ram addresses.
HT46R92 rev. 1.10 13 november 5, 2008 accumulator  acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register  pcl to provide additional program control functions, the low byte of the program counter is made accessible to pro - grammers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily imple - mented. loading a value directly into this pcl register will cause a jump to the specified program memory lo - cation, however, as the register is only 8-bit wide, only jumps within the current program memory page are per- mitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers  tblp, tblh these two special function registers are used to control operation of the look-up table which is stored in the pro- gram memory. tblp is the table pointer and indicates the location where the table data is located. its value must be setup before any table read commands are ex - ecuted. its value can be changed, for example using the  inc  or  dec  instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user de - fined location. status register  status this 8-bit register contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). these arithmetic/logical operation and system manage - ment flags are used to record the status and operation of the microcontroller. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addition, opera - tions related to the status register may give different re - sults due to the different instruction operations. the to flag can be affected only by a system power-up, a wdt time-out or by executing the  clr wdt  or  halt  in - struction. the pdf flag is affected only by executing the  halt  or  clr wdt  instruction or during a system power-up. the z, ov, ac and c flags generally reflect the status of the latest operations.  c is set if an operation results in a carry during an ad - dition operation or if a borrow does not take place dur - ing a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction.  ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nib- ble into the low nibble in subtraction; otherwise ac is cleared.  z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared.  ov is set if an operation results in a carry into the high- est-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared.  pdf is cleared by a system power-up or executing the  clr wdt  instruction. pdf is set by executing the  halt  instruction.  to is cleared by a system power-up or executing the  clr wdt  or  halt  instruction. to is set by a wdt time-out.   )  6  % 8 &                                         !       #  c   &  <     #    #  c   8     c       c   $  c    "     #        !    )  $     $  c   
  
     
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HT46R92 rev. 1.10 14 november 5, 2008 in addition, on entering an interrupt sequence or execut - ing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. interrupt control registers  intc0, intc1 these 8-bit registers, known as intc0 and intc1, con - trol the operation of both the external and internal inter - rupts. by setting various bits within these registers using standard bit manipulation instructions, the enable/dis - able function of the external interrupts and each of the internal interrupts can be independently controlled. a master interrupt bit within these registers, the emi bit, acts like a global enable/disable and is used to set all of the interrupt enable bits on or off. this bit is cleared when an interrupt routine is entered to disable further in - terrupt and is set by executing the reti  instruction. timer/event counter registers  tmr, tmrc the device contains one integrated 8-bit count up timer/ event counter. it has associated registers known as tmr, where the timer
s values are located. one as - sociated control register, known as tmrc contains the setup information for the timer. note that all timer regis- ters can be directly written to in order to preload their contents with fixed data to allow different time intervals to be setup. input/output ports and control registers within the area of special function registers, the i/o registers and their associated control registers play a prominent role. all i/o and output ports have a desig- nated register correspondingly labeled as pa, pb, pc, pd and pe. these labeled i/o registers are mapped to specific addresses within the data memory as shown in the data memory table, which are used to transfer the appropriate output or input data on that port. for the i/o ports, pa and pb, there is an associated control register labeled pac and pbc, also mapped to specific ad - dresses with the data memory. the control register specifies which pins of that port are set as inputs and which are set as outputs. to setup a pin as an input, the corresponding bit of the control register must be set high, for an output it must be set low. during program ini - tialisation, it is important to first setup the control regis - ters to specify which pins are outputs and which are inputs before reading data from or writing data to the i/o ports. one flexible feature of these registers is the ability to directly program single bits using the  set [m].i  and  clr [m].i  instructions. the ability to change i/o pins from output to input and vice versa by manipulating spe - cific bits of the i/o control registers during normal pro - gram operation is a useful feature of these devices. pc, pd and pe are output ports only and therefore do not have control registers. setting its output register high which effectively places its nmos output transistor in high impedance state. re - setting output register to low will force to output low state. pulse width modulator registers  pwm0, pwm1 the device contains two pulse width modulators. each one has its own related independent control register, with the names, pwm0 and pwm1. the 8-bit contents of these registers, defines the duty cycle value for the modulation cycle of the corresponding pulse width modulator. a/d converter registers  adrl, adrh, adcr, acsr the device contains a 6-channel 12-bit a/d converter. the correct operation of the a/d requires the use of two data registers, a control register and a clock source reg - ister. a high byte data register known as adrh, and a low byte data register known as adrl. these are the register locations where the digital value is placed after the completion of an analog to digital conversion cycle. the channel selection and configuration of the a/d con - verter is setup via the control register adcr while the a/d clock frequency is defined by the clock source reg- ister, acsr. mode register  mode the mode register is used to select the mode of opera- tion which can be either normal, slow or power-down. it also contains a bit to control the quick start up function of the 32768hz oscillator. lcd control register  lcdc the lcdc register is used to setup various functions for the lcd display. functions such as 1 / 2 bias enable for each com line, bias resistor and lcd enable are setup with this register. input/output ports holtek microcontrollers offer considerable flexibility on their i/o ports. with the input or output designation of pa, pb pin fully under user program control, pull-high options and wake-up options on pa pins, the user is pro - vided with an i/o structure to meet the needs of a wide range of application possibilities. the device offers up to 16 bidirectional input/output lines on ports pa and pb. there are also outputs on ports pc, pd and pe. these i/o ports are mapped to the data memory with specific addresses as shown in the special purpose data memory table. for input oper - ation, these ports are non-latching, which means the in - puts must be ready at the t2 rising edge of instruction
HT46R92 rev. 1.10 15 november 5, 2008  mov a,[m]  , where m denotes the port address. for output operation, all the data is latched and remains un - changed until the output latch is rewritten. pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an exter - nal resistor. to eliminate the need for these external re - sistors, all pins on port a, when configured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selectable via a configuration option and are imple - mented using a weak pmos transistor. port a wake-up each device has a halt instruction enabling the microcontroller to enter a power down mode and pre - serve power, a feature that is important for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low. after a halt instruction forces the microcontroller into entering a power down condition, the device will re - main in a low-power state until a port a pin receives a high to low going edge. this function is especially suit - able for applications that can be woken up via external switches. note that each pin on port a can be selected individually to have this wake-up feature. i/o port control registers as pa and pb are i/o ports, they each have a port con- trol register, known as pac and pbc, to control the in- put/output configuration. with these control registers, each cmos output or input on these ports with or with- out pull-high resistor structures can be reconfigured dy - namically under configuration option. each pin of the i/o ports is directly mapped to a bit in its associated port control register. for the i/o pin to function as an input, the corresponding bit of the control register must be writ - ten as a  1  . this will then allow the logic state of the in - put pin to be directly read by instructions. when the corresponding bit of the control register is written as a  0  , the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pin-shared functions the flexibility of the microcontroller range is greatly en - hanced by the use of pins that have more than one func - tion. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be over - come. for some pins, the chosen function of the multi-function i/o pins is set by configuration options while for others the function is set by application pro - gram control.  external interrupt input the external dual edge triggered interrupt pin int is pin-shared with the output pin pd0. the pin can be configured as an external interrupt pin if the corre - sponding exte rnal interrupt enable bit in the intc0 reg - ister has been set and the pd0 output is disabled by setting the lcden bit in the lcdc register to zero and the pd0 bit set high. if the external interrupt enable bit is not set then the pin can be used as a pd0 cmos output pin.  external timer clock input the external timer pin tmr is pin-shared with the i/o pins pa2. to configure this pin to operate as timer in - put, the corresponding control bits in the timer control register must be correctly set. for applications that do not require an external timer input, this pin can be used as normal i/o pin. note that if used as normal i/o pin the timer mode control bits in the timer control reg - ister must select the timer mode, which has an internal clock source, to prevent the input pin from interfering with the timer operation.  pwm outputs the devices contain two pwm outputs pwm0 and pwm1 are pin shared with pins pa4 and pa5, respec- tively. the pwm output functions are chosen via con- figuration options and remain fixed after the device is programmed. note that the corresponding bit or bits of the port control register, pac, must setup the pin as an output to enable the pwm output. if the pac port con- trol register has setup the pin as an input, then the pin will function as a normal logic input with the usual pull-high option, even if the pwm configuration option has been selected.  a/d inputs the device has 6 a/d converter inputs. all of these an - alog inputs are pin-shared with i/o pins on port b. if these pins are to be used as a/d inputs and not as normal i/o pins then the corresponding bits in the a/d converter control register, adcr, must be properly set. there are no configuration options associated with the a/d function. if used as i/o pins, then full pull-high resistor configuration options remain, how - ever if used as a/d inputs then any pull-high resistor options associated with these pins will be automati - cally disconnected. i/o pin structures the following diagrams illustrate the i/o pin internal structures. as the exact logical construction of the i/o pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins.
HT46R92 rev. 1.10 16 november 5, 2008 programming considerations within the user program, one of the first things to con - sider is port initialisation. after a reset, all of the i/o data (except pc) and port control registers will be set high. this means that all of the pc, pd and pe output pins will be in a output floating condition. also all the pa and pb i/o pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. if the port control registers, pac and pbc, are then programmed to setup some pins as outputs, these output pins will have an ini - tial high output value unless the associated port data registers, pa and pb, are first programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the  set [m].i  and  clr [m].i  instructions. note that when using these bit control instructions, a read-modify-write opera - tion takes place. the microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the power down mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function. %   ) & 1 " ' 8 ) & 2 " ' 8 ) & - "    ) & , ) & 3 " )   1 ) & 4 " )   2 ) & / ) & .   e  *    !   !
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HT46R92 rev. 1.10 18 november 5, 2008 lcd driver function the device contains circuitry to control an external lcd. this function is controlled using the lcdc register. lcd driver operation when the lcden bit in the lcdc register is set high and pb is configured as an output, ports pb, pc, pd and pe become cmos outputs, but have lower sink/source capabilities making them suitable for lcd segment driving. following a power-on reset, port pb will be setup as an input port, while pc is setup as a pmos output port while pd and pe are setup as nmos output ports, making them suitable for led driving. however at this time, as the lcden bit is low, the pc, pd and pe outputs will be in an open-drain high-impedance condition. to setup ports pb~pe as cmos outputs, the lcden bit must be set high. it is im - portant to note that pb and pc have a lower sink ability (i ol2 ) while pd and pe have a lower driving ability (i oh3 ). the d.c. characteristics provide for further infor- mation. 1 / 2 bias lcd control as the device may be conveniently used for driving lcd panels, pins pc4~pc7 and other i/o ports can be used together to implement 1 / 2 bias lcd timing signals. com0~3 can be sourced from the pc4~7 pins while the segments can be sourced from other i/o ports. the internal 1 / 2 bias circuit is enabled via a combination of the lcden and com0en~com3en bits in the lcdc register. the rsel bit in the lcdc register selects the bias circuit resistor values which should be chosen ac - cording to the actual lcd panel used and to minimise current consumption. note that there is only one bias circuit which is shared by all the com outputs. lcdc register 1 / 2 bias on/off lcden com3en com2en com1en com0en 0xxxxoff 10000off 10001on : : : : : : : : : : on 11111on 1/2 bias circuit control the following steps can be used to implement lcd timing:  select the bias resistor by setting rsel=0 or 1  set lcden=1  use software to generate the vdd, vss, vdd/2 volt- ages by changing com pins pc4~7 to output high, output low and input respectively.  generate the segment timing using other i/o ports with outputs equal to either vss or vdd  2  -  ,  3  2  -  ,  3   
 
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HT46R92 rev. 1.10 19 november 5, 2008 timer/event counters the provision of timers form an important part of any microcontroller, giving the designer a means of carrying out time related functions. the device contains one 8-bit count up timers. with three different operating modes, the timers can be configured to operate as a general timer, an external event counter or as a pulse width measurement device. the provision of a prescaler in the input clock circuitry of each timer/event counter gives added range to the timer. there are two types of registers related to the timer/event counter. the first is the register that con - tains the actual value of the timer and into which an ini - tial value can be preloaded. reading from this register retrieves the contents of the timer/event counter. the second type of associated register is the timer control register which defines the timer options and determines how the timer is to be used. the devices can have the timer clock configured to come from the internal clock source. in addition, the timer clock source can also be configured to come from an external timer pin. configuring the timer/event counter input clock source the internal timer
s clock can originate from various sources, chosen via a configuration option. the internal clock input timer source is used when the timer is in the timer mode or in the pulse width measurement mode. the clock timer source is also first divided by a prescaler, the division ratio of which is conditioned by the timer control register bits psc0~psc2. an external clock source is used when the timer is in the event counting mode, the clock source being provided on the external timer tmr pin. depending upon the con- dition of the te bit, each high to low, or low to high transi - tion on the external timer pin will increment the counter by one. timer register  tmr the timer register are special function register location within the special purpose data memory where the ac - tual timer value is stored. this register has the name tmr. the value in the timer registers increases by one each time an internal clock pulse is received or an exter - nal transition occurs on the external timer pin. the timer will count from the initial value loaded by the preload register to the full count value of ffh at which point the timer overflows and an internal interrupt signal gener - ated. the timer value will then be reset with the initial preload register value and continue counting. to achieve a maximum full range count of ffh the preload register must first be cleared to 00h. it should be noted that after power-on the preload register will be in an un - known condition. note that if the timer/event counter is not running and data is written to its preload register, this data will be immediately written into the actual counter. however, if the counter is enabled and counting, any new data written into the preload register during this pe - riod will remain in the preload register and will only be written into the actual counter the next time an overflow occurs. timer control register  tmrc the flexible features of the holtek microcontroller timer/ event counters enable them to operate in three different modes, the options of which are determined by the con - tents of their respective control register. the device con - tains one timer control register known as tmrc. it is the timer control register together with its corresponding timer registers that control the full operation of the timer/event counters. before the timer can be used, it is essential that the timer control register is fully pro- grammed with the right data to ensure its correct opera- tion, a process that is normally carried out during program initialisation. to choose which of the three modes the timer is to oper- ate in, either in the timer mode, the event counting mode or the pulse width measurement mode, bits 7 and 6 of the timer control register, which are known as the bit pair tm1/tm0 respectively, must be set to the required logic levels. the timer-on bit, which is bit 4 of the timer control register and known as ton, provides the basic on/off control of the respective timer. setting the bit high allows the counter to run, clearing the bit stops the coun - ter. the timer/event counters also contains a prescaler function, with bits 0~2 of the associated timer control register determining the division ratio of the input clock.      c  5    e   c    
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HT46R92 rev. 1.10 20 november 5, 2008 the prescaler bit settings have no effect if an external clock source is used. if the timer is in the event count or pulse width measurement mode, the active transition edge level type is selected by the logic level of bit 3 of the timer control register which is known as te. configuring the timer mode in this mode, the timer/event counter can be utilised to measure fixed time intervals, providing an internal inter- rupt signal each time the counter overflows. to operate in this mode, the operating mode select bit pair in the appropriate timer control register must be set to the correct value as shown. control register operating mode select bits for the timer mode bit7 bit6 10 in this mode, a choice of internal clocks can be used as the timer/event counter clock. however, this clock source is further divided by a prescaler, the value of which is determined by the prescaler rate select bits, which are bits 0~2 in the respective timer control reg - ister. after the other bits in the timer control register have been setup, the enable bit, which is bit 4 of the timer control register, can be set high to enable the timer/event counter to run. each time an internal clock cycle occurs, the timer/event counter increments by one. when it is full and overflows, an interrupt signal is generated and the timer/event counter will reload the value already loaded into the preload register and con- tinue counting. the interrupt can be disabled by ensur- ing that the timer/event counter interrupt enable bit in the interrupt control register, is reset to zero. configuring the event counter mode in this mode, a number of externally changing logic events, occurring on the external timer pins, can be re - corded by the timer/event counters. to operate in this mode, the operating mode select bit pair in the appro - priate timer control register must be set to the correct value as shown. control register operating mode select bits for the event counter mode bit7 bit6 01 in this mode the external timer pins are used as the timer/event counter clock source, however it is not di - vided by the internal prescaler. after the other bits in the appropriate timer control register have been setup, the enable bit, which is bit 4 of the timer control regis - ter, can be set high to enable the timer/event counter to run. if the active edge select bit, which is bit 3 of the ap -  #  $         5 
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HT46R92 rev. 1.10 21 november 5, 2008 propriate timer control register, is low, the timer/eventcounter will increment each time the asso - ciated external timer pin receives a low to high transi - tion. if the active edge select bit is high, the timer/event counter will increment each time the exter - nal timer pin receives a high to low transition. when it is full and overflows, an interrupt signal is generated and the timer/event counter will reload the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the asso - ciated timer/event counter interrupt enable bit in the interrupt control register, is reset to zero. as the external timer pin is shared with an i/o pin, to en - sure that the pin is configured to operate as an event counter input pin, two things have to happen. the first is to ensure that the operating mode select bits in the timer control register place the timer/event counter in the event counting mode, the second is to ensure that the port control register configures the pin as an input. it should be noted that in the event counting mode, even if the microcontroller is in the power down mode, the timer/event counter will continue to record externally changing logic events on the timer input pin. as a result when the timer overflows it will generate a timer interrupt and corresponding wake-up source. configuring the pulse width measurement mode in this mode, the timer/event counter can be utilised to measure the width of external pulses applied to the ex - ternal timer pins. to operate in this mode, the operating mode select bit pair in the appropriate timer control register must be set to the correct value as shown. control register operating mode select bits for the pulse width measurement mode bit7 bit6 11 in this mode, a choice of internal clocks can be used as the timer/event counter clock. however this clock source is further divided by a prescaler, the value of which is determined by the prescaler rate select bits, which are bits 0~2 in the respective timer control reg - ister. after the other bits in the appropriate timer con - trol register have been setup, the enable bit, which is bit 4 of the timer control register, can be set high to en - able the timer/event counter, however it will not actu - ally start counting until an active edge is received on the external timer pin. if the active edge select bit, which is bit 3 of the timer control register, is low, once a high to low transition has been received on the related external timer pin, the timer/event counter will start counting until the external timer pin returns to its original high level. at this point the enable bit will be automatically reset to zero and the timer/event counter will stop counting. if the active edge select bit is high, the timer/event counter will be - gin counting once a low to high transition has been re- ceived on the external timer pin and stop counting when the external timer pin returns to its original low level. as before, the enable bit will be automatically reset to zero and the timer/event counter will stop counting. it is im- portant to note that in the pulse width measurement mode, the enable bit is automatically reset to zero when the external control signal on the external timer pin re- turns to its original level, whereas in the other two modes the enable bit can only be reset to zero under program control. the residual value in the timer/event counter, which can now be read by the program, therefore represents the length of the pulse received on the external timer pin. as the enable bit has now been reset, any further transitions on the external timer pin will be ignored. not until the enable bit is again set high by the program can = 2 = - = , = 3       <
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HT46R92 rev. 1.10 22 november 5, 2008 the timer begin further pulse width measurements. in this way, single shot pulse measurements can be easily made. it should be noted that in this mode the timer/event counter is controlled by logical transitions on the exter - nal timer pin and not by the logic level. when the timer/event counter is full and overflows, an interrupt signal is generated and the timer/event counter will re - load the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the interrupt control register is reset to zero. as the external timer pin is shared with an i/o pin, to en - sure that the pin is configured to operate as pulse width measurement pins, two things have to happen. the first is to ensure that the operating mode select bits in the timer control register place the related timer/event counter in the pulse width measurement mode. the second is to ensure that the port control register configures the timer pin as an input. prescaler bits psc0~psc2 of the tmrc register can be used to define the pre-scaling stages of the internal clock source for the timer/event counters. in the event counter mode the prescaler has no effect. i/o interfacing the timer/event counter, when configured to run in the event counter or pulse width measurement mode, re- quires the use of the external pa2/tmr pin for correct operation. as this pin is a shared pin it must be config- ured correctly to ensure it is setup for use as a timer/event counter input and not as a normal i/o pin. this is implemented by ensuring that the mode select bits in the timer/event counter control register, select either the event counter or pulse width measurement mode. additionally the port control register pac bit 2 must be set high to ensure that the pin is setup as an in - put. any pull-high resistor configuration option on this pin will remain valid even if the pin is used as a timer/event counter input. programming considerations when configured to run in the timer mode, one of the in - ternal clocks is used as the timer clock source and is therefore synchronised with the overall operation of the microcontroller. in this mode when the appropriate timer register is full, the microcontroller will generate an inter - nal interrupt signal directing the program flow to the re - spective internal interrupt vector. for the pulse width measurement mode, one of the internal system clocks is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. as this is an external event and not synchronised with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. as a result, there may be small differences in measured values requiring pro - grammers to take this into account during programming. the same applies if the timer is configured to be in the event counting mode, which again is an external event and not synchronised with the internal system or timer clock. when the timer/event counter is read, or if data is writ - ten to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. care must be taken to ensure that the timers are properly in - itialised before using them for the first time. the associ - ated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. the edge select, timer mode and clock source control bits in timer control regis - ter must also be correctly set to ensure the timer is prop - erly configured for the required application. it is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer reg- isters are unknown. after the timer has been initialised the timer can be turned on and off by controlling the en- able bit in the timer control register. note that setting the timer enable bit high to turn the timer on, should only be executed after the timer mode bits have been properly setup. setting the timer enable bit high together with a mode bit modification, may lead to improper timer oper- ation if executed as a single timer control register byte write instruction. when the timer/event counter overflows, its corre - sponding interrupt request flag in the interrupt control register will be set. if the timer interrupt is enabled this will in turn generate an interrupt signal. however irre - spective of whether the interrupts are enabled or not, a timer/event counter overflow will also generate a wake-up signal if the device is in a power-down condi - tion. this situation may occur if the timer/event counter is in the event counting mode and if the external signal continues to change state. in such a case, the timer/event counter will continue to count these exter - nal events and if an overflow occurs the device will be woken up from its power-down condition. to prevent such a wake-up from occurring, the timer interrupt re - quest flag should first be set high before issuing the halt instruction to enter the power down mode.
HT46R92 rev. 1.10 23 november 5, 2008 timer program example this program example shows how the timer/event counter registers are setup, along with how the interrupts are en - abled and managed. note how the timer/event counter is turned on, by setting bit 4 of the tmrc as an independent instruction. the timer/ event counter can be turned off in a similar way by clearing the same bit. this example program sets the timer/event counter to be in the timer mode, which uses the internal system clock as the clock source. org 04h ; external interrupt vector reti org 08h ; timer/event counter interrupt vector jmp tmrint0 ; jump here when timer/event counter overflows : org 20h ; main program ;internal timer/event counter interrupt routine tmrint0: : ; timer/event counter main program placed here : reti : : begin: ;setup timer registers mov a,09bh ; setup timer preload value mov tmr,a; mov a,081h ; setup timer control register mov tmrc,a ; timer mode and prescaler set to /4 ; setup interrupt register mov a,005h ; enable master and timer/event counter interrupt mov intc0,a set tmrc.4 ; start timer/event counter - note mode bits must be previously setup pulse width modulator the device contains two pulse width modulation, pwm, outputs, known as pwm0 and pwm1. useful for such applications such as motor speed control, the pwm function provides an output with a fixed frequency but with a duty cycle that can be varied by setting particular values into the corresponding pwm registers. channels pwm mode output pins register name 2 6+2 or 7+1 pa4 pa5 pwm0 pwm1 pwm overview the pwm outputs are selected via configuration op - tions. two registers, located in the data memory are as - signed to the pulse width modulator and are known as pwm0 and pwm1. it is in these registers that the 8-bit value, which represents the overall duty cycle of one modulation cycle of the output waveform, should be placed. to increase the pwm modulation frequency, each modulation cycle is modulated into two or four indi - vidual modulation sub-sections, known as the 7+1 mode or the 6+2 mode respectively. the device can choose which mode to use by selecting the appropriate configu - ration option. note that it is only necessary to write the required modulation value into the corresponding pwm0 or pwm1 register as the subdivision of the wave- form into its sub-modulation cycles is implemented au- tomatically within the microcontroller hardware. the pwm clock source is the system clock f sys . this method of dividing the original modulation cycle into a further 2 or 4 sub-cycles enables the generation of higher pwm frequencies, which allow a wider range of applications to be served. as long as the periods of the generated pwm pulses are less than the time constants of the load, the pwm output will be suitable as such long time constant loads will average out the pulses of the pwm output. the difference between what is known as the pwm cycle frequency and the pwm modulation fre - quency should be understood. as the pwm clock is the system clock, f sys , and as the pwm value is 8-bits wide, the overall pwm cycle frequency is f sys /256. however, when in the 7+1 mode of operation, the pwm modulation frequency will be f sys /128, while the pwm modulation frequency for the 6+2 mode of operation will be f sys /64. 6+2 pwm mode each full pwm cycle, as it is controlled by an 8-bit regis - ter, has 256 clock periods. however, in the 6+2 pwm mode, each pwm cycle is subdivided into four individual sub-cycles known as modulation cycle 0~modulation cycle 3, denoted as  i  in the table. each one of these
HT46R92 rev. 1.10 24 november 5, 2008 four sub-cycles contains 64 clock cycles. in this mode, a modulation frequency increase by a factor of four is achieved. the 8-bit pwm register value, which repre - sents the overall duty cycle of the pwm waveform, is di - vided into two groups. the first group which consists of bit2~bit7 is denoted here as the dc value. the second group which consists of bit0~bit1 is known as the ac value. in the 6+2 pwm mode, the duty cycle value of each of the four modulation sub-cycles is shown in the following table. parameter ac (0~3) dc (duty cycle) modulation cycle i (i=0~3) i  " - )   a )   b  i 2 1 1 a )   b  i 2 1 2 )   a )   b  i 2 1 - )   a )   b  i 2 1 , )   )    #    ?  - 4 / " c  >  - 4 " / 3 - / " / 3 - / " / 3 - / " / 3 - 4 " / 3 - 4 " / 3 - 4 " / 3 - 4 " / 3 - 4 " / 3 - 4 " / 3 - 4 " / 3 - / " / 3 - / " / 3 - 4 " / 3 - 4 " / 3 - / " / 3 - 4 " / 3 - / " / 3 - / " / 3 - / " / 3    
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   #    1 7+1 pwm mode pwm1 output pin is setup as an output. after these two initial steps have been carried out, and of course after the required pwm value has been written into the pwm0 or pwm1 register, writing a  1  to the corre - sponding pa.4 or pa.5 bit in the pa output data register will enable the pwm data to appear on the pin. writing a  0  to the bit will disable the pwm output function and force the output low. in this way, the port a data output register bits, pa.4 and pa.5, can be used as an on/off control for the pwm function. note that if the configura - tion options have selected the pwm function, but a  1  has been written to its corresponding bit in the pac con - trol register to configure the pin as an input, then the pin can still function as a normal input line, with pull-high re - sistor options. pwm programming example the following sample program shows how the pwm outputs are setup and controlled. before use the corre - sponding pwm output configuration options must first be selected. mov a,64h ; setup pwm0 value of 100 decimal which is 64h mov pwm0,a clr pac.4 ; setup pin pa4 as an output set pa.4 ; pa.4=1; enable the pwm output :: :: clr pa.4 ; disable the pwm output  pa4 will remain low
HT46R92 rev. 1.10 26 november 5, 2008 analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however, to properly process these signals by a microcontroller, they must first be converted into digital signals by a/d converters. by integrating the a/d con - version electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. a/d overview the device contains a 6-channel analog to digital con - verter which can directly interface to external analog sig - nals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. input channels conversion bits input pins 6 12 pb0~pb5 the accompanying diagram shows the overall internal structure of the a/d converter, together with its associ - ated registers. a/d converter data registers  adrl, adrh as the device contains a 12-bit a/d converter, it requires two data registers to store its conversion value, a high byte register, known as adrh, and a low byte register, known as adrl. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. only the high byte register, adrh, utilises its full 8-bit contents. the low byte register utilises only 4 bits of its 8-bit contents as it contains only the lowest bit of the 12-bit converted value. in the following tables, d0~d11 are the a/d conversion data result bits. register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adrl d3 d2 d1 d0  adrh d11 d10 d9 d8 d7 d6 d5 d4 a/d data registers a/d converter control register  adcr to control the function and operation of the a/d con - verter, a control register known as adcr is provided. this 8-bit register defines functions such as the selec - tion of which analog channel is connected to the internal a/d converter, which pins are used as analog inputs and which are used as normal i/os as well as controlling the start function and monitoring the a/d converter end of conversion status. one section of this register contains the bits acs2~acs0 which define the channel number. as each of the devices contains only one actual analog to digital converter circuit, each of the individual 8 analog inputs must be routed to the converter. it is the function of the acs2~acs0 bits in the adcr register to determine which analog channel is actually connected to the inter- nal a/d converter. the adcr control register also contains the pcr2~pcr0 bits which determine which pins on port b are used as analog inputs for the a/d converter and which pins are to be used as normal i/o pins. if the 3-bit address on pcr2~pcr0 has a value of  110  or  111  , then all six pins, namely an0~an5 will all be set as ana- log inputs. note that if the pcr2~pcr0 bits are all set to zero, then all the port b pins will be setup as normal i/os and the internal a/d converter circuitry will be powered off to reduce the power consumption. &         c  >   5 &         
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HT46R92 rev. 1.10 27 november 5, 2008 the start bit in the adcr register is used to start and reset the a/d converter. when the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. when the start bit is brought from low to high but not low again, the eocb bit in the adcr register will be set to a  1  and the analog to digital converter will be reset. it is the start bit that is used to control the overall on/off opera - tion of the internal analog to digital converter. the eocb bit in the adcr register is used to indicate when the analog to digital conversion process is com - plete. this bit will be automatically set to  0  by the microcontroller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request flag will be set in the interrupt control register, and if the inter - rupts are enabled, an appropriate internal interrupt sig - nal will be generated. this a/d internal interrupt signal will direct the program flow to the associated a/d inter - nal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr register to check whether it has been cleared as an alternative method of detect - ing the end of an a/d conversion cycle. a/d converter power control as an integrated circuit function within the device, the a/d converter will naturally consume a limited amount of power. however to provide users with a means of on/off control to reduce power consumption, two methods are provided. one means of turning off the a/d converter circuitry is to ensure that the pcr0~pcr2 bits in the adcr register are cleared to zero. another method is to use the adonb bit in the acsr register, which if set high will also turn off the a/d internal circuitry. both power off methods are independent and have overriding control over the other. pcr bits adonb bit a/d circuits 0 x off >0 0 on > 0 1 off a/d power control it should be noted that the power supply to the a/d con - verter is supplied via the vdd pin. however the lowest operating voltage of the analog circuitry is higher than that of the digital circuitry and therefore the analog cir - cuits will fail to operate at the lower end of the vdd specification. the dc characteristics therefore specify a separate operating voltage specification for the analog circuitry. a/d converter clock source register  acsr the clock source for the a/d converter, which originates from the system clock f sys , is first divided by a division ratio, the value of which is determined by the adcs1 and adcs0 bits in the acsr register.  .  1   &   )   - )   2 )   1 &   - &   2 &   1    
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HT46R92 rev. 1.10 28 november 5, 2008 f sys a/d clock period (t ad ) adcs2, adcs1, adcs0=000 (f sys /2) adcs2, adcs1, adcs0=001 (f sys /8) adcs2, adcs1, adcs0=010 (f sys /32) adcs2, adcs1, adcs0=011 1mhz 2  s8  s32  s undefined 2mhz 1  s4  s16  s undefined 4mhz 500ns* 2  s8  s undefined 8mhz 250ns* 1  s4  s undefined a/d clock period examples although the a/d clock source is determined by the sys- tem clock f sys , and by bits adcs1 and adcs0, there are some limitations on the maximum a/d clock source speed that can be selected. as the minimum value of permissible a/d clock period, t ad ,is0.5  s, care must be taken for sys - tem clock speeds in excess of 4mhz. for system clock speeds in excess of 4mhz, the adcs1 and adcs0 bits should not be set to  00  . doing so will give a/d clock peri - ods that are less than the minimum a/d clock period which may result in inaccurate a/d conversion values. refer to the accompanying table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specified minimum a/d clock period. a/d input pins all of the a/d analog input pins are pin-shared with the i/o pins on port b. bits pcr2~pcr0 in the adcr regis - ter, not configuration options, determine whether the in - put pins are setup as normal port b input/output pins or whether they are setup as analog inputs. in this way, pins can be changed under program control to change their function from normal i/o operation to analog inputs and vice versa. pull-high resistors, which are setup through configuration options, apply to the input pins only when they are used as normal i/o pins, if setup as a/d inputs the pull-high resistors will be automatically disconnected. note that it is not necessary to first setup the a/d pin as an input in the pbc port control register to enable the a/d input as when the pcr2~pcr0 bits enable an a/d input, the status of the port control register will be overridden. the a/d reference voltage is supplied on an individual vref pin and can be connected to an external reference voltage source. appropriate measures should be taken to ensure that the vref voltage does not exceed the vdd voltage level and that it remains as stable and noise free as possible. initialising the a/d converter the internal a/d converter must be in a special way. each time the port b a/d channel selection bits are modi - fied by the program, the a/d converter must be re-initialised. if the a/d converter is not initialised after the channel selection bits are changed, the eocb flag may have an undefined value, which may produce a false end of conversion signal. to initialise the a/d converter after the channel selection bits have changed, then, within a time frame of one to ten instruction cycles, the start bit in the adcr register must first be set high and then im - mediately cleared to zero. this will ensure that the eocb flag is correctly set to a high condition.  $              
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HT46R92 rev. 1.10 29 november 5, 2008 summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/d con - version process.  step 1 select the required a/d conversion clock by correctly programming bits adcs1 and adcs0 in the acsr register.  step 2 enable the a/d by clearing the adonb bit in the acsr register.  step 3 select which channel is to be connected to the internal a/d converter by correctly programming the acs2~acs0 bits which are also contained in the adcr register.  step 4 select which pins on port b are to be used as a/d in - puts and configure them as a/d input pins by correctly programming the pcr0~pcr2 bits in the adcr reg - ister. note that this step can be combined with step 2 into a single adcr register programming operation.  step 5 if the interrupts are to be used, the interrupt control reg - isters must be correctly configured to ensure the a/d converter interrupt function is active. the master inter - rupt control bit, emi, in the intc interrupt control regis - ter must be set to  1  and the a/d converter interrupt bit, eadi, in the intc register must also be set to  1  .  step 6 the analog to digital conversion process can now be initialised by setting the start bit in the adcr regis - ter from  0  to  1  and then to  0  again. note that this bit should have been originally set to  0  .  step 7 to check when the analog to digital conversion pro - cess is complete, the eocb bit in the adcr register can be polled. the conversion process is complete when this bit goes low. when this occurs the a/d data registers adrl and adrh can be read to obtain the conversion value. as an alternative method, if the in - terrupts are enabled and the stack is not full, the pro - gram can wait for an a/d interrupt to occur. note: when checking for the end of the conversion process, if the method of polling the eocb bit in the adcr register is used, the interrupt enable step above can be omitted. the accompanying timing diagram shows graphically the various stages involved in an analog to digital con- version process and its associated timing. the setting up and operation of the a/d converter func- tion is fully under the control of the application program as there are no configuration options associated with the a/d converter. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. the time taken for the a/d conversion is 16t ad where t ad is equal to the a/d clock period. programming considerations when programming, special attention must be given to the a/d channel selection bits in the adcr register. if these bits are all cleared to zero no external pins will be selected for use as a/d input pins allowing the pins to be used as normal i/o pins. when this happens the power supplied to the internal a/d circuitry will be turned off re - sulting in a reduction of supply current. this ability to re - duce power by turning off the internal a/d function by clearing the a/d channel selection bits may be an impor - tant consideration in battery powered applications. the a/d can also be turned off by using the adonb bit int he acsr register.
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HT46R92 rev. 1.10 30 november 5, 2008 another important programming consideration is that when the a/d channel selection bits change value, the a/d con - verter must be . this is achieved by pulsing the start bit in the adcr register immediately after the channel selection bits have changed state. the exception to this is where the channel selection bits are all cleared, in which case the a/d converter is not required to be re-initialised. a/d programming example the following two programming examples illustrate how to setup and implement an a/d conversion. in the first exam - ple, the method of polling the eocb bit in the adcr register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an eocb polling method to detect the end of conversion clr eadi ; disable adc interrupt mov a,00000001b mov acsr,a ; setup the acsr register to select f sys /8 as ; the a/d clock mov a,00100000b ; setup adcr register to configure port pb0~pb3 ; as a/d inputs mov adcr,a ; and select an0 to be connected to the a/d ; converter : : ; as the port b channel bits have changed the ; following start ; signal (0-1-0) must be issued within 10 ; instruction cycles : start_conversion: clr start set start ; reset a/d clr start ; start a/d polling_eoc: sz eocb ; poll the adcr register eocb bit to detect end ; of a/d conversion jmp polling_eoc ; continue polling mov a,adrl ; read low byte conversion result value mov adrl_buffer,a ; save result to user defined register mov a,adrh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defined register : jmp start_conversion ; start next a/d conversion example: using the interrupt method to detect the end of conversion clr eadi ; disable adc interrupt mov a,00000001b mov acsr,a ; setup the acsr register to select fsys/8 as ; the a/d clock mov a,00100000b ; setup adcr register to configure port pb0~pb3 ; as a/d inputs mov adcr,a ; and select an0 to be connected to the a/d : ; as the port b channel bits have changed the ; following start signal(0-1-0) must be issued ; within 10 instruction cycles : start_conversion: clr start set start ; reset a/d clr start ; start a/d clr adf ; clear adc interrupt request flag set eadi ; enable adc interrupt set emi ; enable global interrupt : : :
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  2 9 4    ' %   6 3 1 7 / ideal a/d transfer function ; adc interrupt service routine adc_isr: mov acc_stack,a ; save acc to user defined memory mov a,status mov status_stack,a ; save status to user defined memory : : mov a,adrl ; read low byte conversion result value mov adrl_buffer,a ; save result to user defined register mov a,adrh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defined register : : exit_int_isr: mov a,status_stack mov status,a ; restore status from user defined memory mov a,acc_stack ; restore acc from user defined memory reti a/d transfer function as the device contain a 12-bit a/d converter, its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the vdd voltage, this gives a single bit analog input value of v dd /4096. the diagram show the ideal transfer function between the analog input value and the digitised output value for the a/d converter. note that to reduce the quantisation error, a 0.5 lsb off - set is added to the a/d converter input. except for the digitised zero value, the subsequent digitised values will change at a point 0.5 lsb below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 lsb below the v dd level.
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 @       d 1 d  1      . f    operation mode register  mode operation mode the device can operate in three different modes which are known as normal, slow and power down. to sup - port these different modes two system clocks are re - quired, an rc or crystal external system oscillator connected to the osc1 and osc2 pins and and a 32768 external crystal oscillator connected to the osc3 and osc4 pins. both system clocks must be con - nected for correct operation. mode selection the choice of which system clock is used is made using the mods bit in the mode register and can be either an rc/xtal oscillator or a 32768hz rtc. selecting the slower 32768hz oscillator by setting the mods bit high will naturally cause the microcontroller to consume less power; this is known as the slow mode. in this mode the rc or crystal oscillator will be turned off. selecting the higher frequency rc or crystal oscillator by setting the mods bit to zero will place the microcontroller in the normal mode. the other mode, known as the power-down mode can only be entered when a halt instruction is executed. note that in all modes the 32768hz oscillator continues to run. if the 32768hz oscillator is chosen as the system clock, then the wdt clock source configuration option must also select the 32768hz oscillator as its clock source, otherwise unpredictable system operation may occur. mode system clock halt instruction mods rc/xtal oscillator 32768hz normal rc/xtal oscillator not executed 0 on on slow 32768hz not executed 1 off on power down halt executed x off on operation mode
HT46R92 rev. 1.10 33 november 5, 2008 interrupts interrupts are an important part of any microcontroller system. when an external event or an internal function such as a timer/event counter, time base or a/d con - verter requires microcontroller attention, their corre - sponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to di - rect attention to their respective needs. each device in this series contains a single external interrupt and sev - eral internal interrupts functions. the external interrupt is controlled by the action of the external int pin, while the internal interrupts are controlled by the timer/event counter overflow, time base overflow interrupt and the a/d converter interrupt. interrupt registers overall interrupt control, which means interrupt enabling and request flag setting, is controlled by the intc0 and intc1 registers, which are located in the data memory. by controlling the appropriate enable bits in this register each individual interrupt can be enabled or disabled. also when an interrupt occurs, the corresponding re - quest flag will be set by the microcontroller. the global enable flag if cleared to zero will disable all interrupts. + ,  $ )          .  1  &   & "       
   
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HT46R92 rev. 1.10 34 november 5, 2008 interrupt operation a timer/event counter overflow, a time base overflow, an end of a/d conversion or the external interrupt line being pulled low will all generate an interrupt request by setting their corresponding request flag, if their appropri - ate interrupt enable bit is set. when this happens, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the correspond - ing interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a jmp statement which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a reti statement, which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their as - sociated request flags, are shown in the following dia - gram with their order of priority. once an interrupt subroutine is serviced, all the other in - terrupts will be blocked, as the emi bit will be cleared au - tomatically. this will prevent any further interrupt nesting from occurring. however, if other interrupt requests oc - cur during this interval, although the interrupt will not be immediately serviced, the request flag will still be re - corded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the rou - tine, to allow interrupt nesting. if the stack is full, the in - terrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. interrupt priority interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in case of simultaneous requests, the following table shows the priority that is applied. these can be masked by resetting the emi bit. interrupt source vector priority external interrupt 04h 1 timer/event counter overflow 08h 2 time base overflow 0ch 3 a/d converter conversion end 10h 4 interrupt priority in cases where both external and internal interrupts are enabled and where an external and internal interrupt oc- curs simultaneously, the external interrupt will always have priority and will therefore be serviced first. suitable masking of the individual interrupts using the intc0 and intc1 registers can prevent simultaneous occurrences. external interrupt for an external interrupt to occur, the global interrupt en - able bit, emi, and external interrupt enable bit, eei, must first be set. an actual external interrupt will take place when the external interrupt request flag, eif in intc0. as the external interrupt is a dual edge triggered type, the eif flag will be set when either a high to low or low to high transition appears on the int line. the external interrupt pin is pin-shared with the output pin pd0 and can only be configured as an external interrupt pin if the correspond - ing external interrupt enable bit in the intc0 register has been set and the pd0 output is disabled by setting the lcden bit in the lcdc register to zero and the pd0 bit set high. if the external interrupt enable bit is not set then the pin can be used as a pd0 cmos output pin. when the interrupt is enabled, the stack is not full and a high to low transition appears on the external interrupt pin, a sub - routine call to the external interrupt vector at location 04h, will take place. when the interrupt is serviced, the external interrupt request flag, eif; bit 4 of intc0 will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. & 
 
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HT46R92 rev. 1.10 35 november 5, 2008 timer/event counter interrupt for a timer/event counter interrupt to occur, the global interrupt enable bit, emi , and the corresponding timer interrupt enable bit, eti in the intc0 register must first be set. an actual timer/event counter interrupt will take place when the timer/event counter interrupt request flag, tf in intc0, is set, a situation that will occur when the relevant timer/event counter overflows. when the interrupt is enabled, the stack is not full and a timer/event counter overflow occurs, a subroutine call to the timer interrupt vector at location 08h will take place for timer/event counter. when the interrupt is serviced, the timer interrupt request flag, tf, will be au - tomatically reset and the emi bit will be automatically cleared to disable other interrupts. time base interrupt for a time base interrupt to occur, the global interrupt enable bit, emi, in the intc0 register, and the time base interrupt enable bit, etbi, in the intc0 register must first be set. an actual time base interrupt will take place when the time base request flag, tbf in intc0 is set, a situation that will occur when the time base over - flows. when the interrupt is enabled, the stack is not full, and a time base overflow occurs, a subroutine call to the time base vector location at 0ch will take place. when the interrupt is serviced, the time base interrupt request flag, tbf, will be automatically reset and the emi bit will be automatically cleared to disable other in- terrupts. a/d interrupt for an a/d interrupt to occur, the global interrupt enable bit, emi, and the corresponding interrupt enable bit, eadi, must be first set. an actual a/d interrupt will take place when the a/d converter request flag, adf in the intc1 register is set, a situation that will occur when an a/d conversion process has completed. when the inter - rupt is enabled, the stack is not full and an a/d conver - sion process finishes execution, a subroutine call to the a/d interrupt vector at location 10h, will take place. when the interrupt is serviced, the a/d interrupt request flag, adf, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. programming considerations by disabling the interrupt enable bits, a requested inter - rupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the intc0 or intc1 register until the corre - sponding interrupt is serviced or until the request flag is cleared by a software instruction. it is recommended that programs do not use the  call subroutine  instruction within the interrupt subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and the interrupt is not well con - trolled, the original control sequence will be damaged once a  call subroutine  is executed in the interrupt subroutine. all of these interrupts have the capability of waking up the processor when in the power down mode. only the program counter is pushed onto the stack. if the contents of the register or status register are altered by the interrupt service program, which may corrupt the desired control sequence, then the contents should be saved in advance.    *         c    
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HT46R92 rev. 1.10 36 november 5, 2008 reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is first applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, af - ter a short delay, will be in a well defined state and ready to execute the first program instruction. after this power-on reset, certain important internal registers will be set to defined states before the program com - mences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the is running. one example of this is where after power has been applied and the microcontroller is al - ready running, the res line is forcefully pulled low. in such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged al - lowing the microcontroller to proceed with normal oper - ation after the reset line is allowed to return high. another type of reset is when the watchdog timer over - flows and resets the microcontroller. all types of reset operations result in different register conditions being setup. another reset exists in the form of a low voltage reset, lvr, where a full reset, similar to the res reset is imple- mented in situations where the power supply voltage falls below a certain threshold. reset functions there are five ways in which a microcontroller reset can occur, through events occurring both internally and ex - ternally:  power-on reset the most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. as well as ensuring that the program memory begins execution from the first memory ad - dress, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. although the microcontroller has an internal rc reset function, if the vdd power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. for this reason it is recom - mended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay, normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the figures stands for system start-up timer. for most applications a resistor connected between vdd and the res pin and a capacitor connected be - tween vss and the res pin will provide a suitable ex - ternal reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for applications that operate within an environment where more noise is present the enhanced reset cir- cuit shown is recommended. more information regarding external reset circuits is located in application note ha0075e on the holtek website.  res pin reset this type of reset occurs when the microcontroller is already running and the res pin is forcefully pulled low by external hardware such as an external switch. in this case as in the case of other reset, the program counter will reset to zero and program execution initi - ated from this point.    %             

       
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HT46R92 rev. 1.10 37 november 5, 2008  low voltage reset  lvr the microcontroller contains a low voltage reset cir - cuit in order to monitor the supply voltage of the de - vice. the lvr function is selected via a configuration option. if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery, the lvr will automatically reset the device internally. for a valid lvr signal, a low sup - ply voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for a time greater than that spec - ified by t lvr in the a.c. characteristics. if the low sup - ply voltage state does not exceed this value, the lvr will ignore the low supply voltage and will not perform a reset function. the actual v lvr value can be se - lected via configuration options.  watchdog time-out reset during normal operation the watchdog time-out reset during normal opera - tion is the same as a hardware res pin reset except that the watchdog time-out flag to will be set to  1  .  watchdog time-out reset during power down the watchdog time-out reset during power down is a little different from other kinds of reset. most of the conditions remain unchanged except that the pro - gram counter and the stack pointer will be cleared to  0  and the to flag will be set to  1  . refer to the a.c. characteristics for t sst details. reset initial conditions the different types of reset described affect the reset flags in different ways. these flags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the power down function or watchdog timer. the reset flags are shown in the table: to pdf reset conditions 0 0 res reset during power-on u u res or lvr reset during normal operation 1 u wdt time-out reset during normal operation 1 1 wdt time-out reset during power down note:  u  stands for unchanged the following table indicates the way in which the vari - ous components of the microcontroller are affected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt clear after reset, wdt begins counting timer/event counter timer counter will be turned off prescaler the timer counter prescaler will be cleared input/output ports i/o ports will be setup as inputs stack pointer stack pointer will point to the top of the stack the different kinds of resets all affect the internal regis - ters of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the accompanying table describes how each type of reset affects each of the microcontroller internal registers.           
          

   wdt time-out reset during power down timing chart           
          

       

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HT46R92 rev. 1.10 38 november 5, 2008 register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (halt) mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh  xxx xxxx  uuu uuuu  uuu uuuu  uuu uuuu status  00 xxxx  uu uuuu  1u uuuu  11 uuuu intc0  000 0000  000 0000  000 0000  uuu uuuu tmr xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmrc 00  0 1000 00  0 1000 00  0 1000 uu  u uuuu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 uuuu uuuu pc 0000 0000 0000 0000 0000 0000 uuuu uuuu pd 1111 1111 1111 1111 1111 1111 uuuu uuuu pe 1111 1111 1111 1111 1111 1111 uuuu uuuu pwm0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu pwm1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu intc1  0  0  0  0  0  0  u  u lcdc  00 0000  00 0000  00 0000  uu uuuu mode  0  0  0  0  0  0  u  u adrl xxxx  xxxx  xxxx  uuuu  adrh xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adcr 0100 0000 0100 0000 0100 0000 uuuu uuuu acsr 10    000 10    000 10    000 1u   uuu  u  stands for unchanged  x  stands for unknown  stands for unimplemented
HT46R92 rev. 1.10 39 november 5, 2008 oscillator various oscillator options offer the user a wide range of functions according to their various application require - ments. three types of system clocks can be selected while various clock source options for the watchdog timer are provided for maximum flexibility. the three methods of generating the system clock are:  external crystal/resonator oscillator  external rc oscillator  external 32768hz oscillator the choice of external crystal/resonator or rc system oscillator is made via a configuration option while the se - lection of the 32768hz oscillator is made using the mods bit in the mode register. the 32768hz oscillator must always be connected along with a choice of either rc or crystal/resonator for correct operation. more information regarding the oscillator is located in application note ha0075e on the holtek website. external crystal/resonator oscillator the simple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feed - back for oscillation, and will normally not require exter - nal capacitors. however, for some crystals and most resonator types, to ensure oscillation and accurate fre- quency generation, it may be necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer
s specifica - tion. the external parallel feedback resistor, rp, is nor - mally not required but in some cases may be needed to assist with oscillation start up. internal ca, cb, rf typical values @ 5v, 25  c ca cb rf 11pf~13pf 13pf~15pf 470k oscillator internal component values crystal oscillator c1 and c2 values crystal frequency c1 c2 cl 12mhz tbd tbd tbd 8mhz tbd tbd tbd 4mhz tbd tbd tbd 1mhz tbd tbd tbd note: 1. c1 and c2 values are for guidance only. 2. cl is the crystal manufacturer specified load capacitor value. crystal recommended capacitor values resonator c1 and c2 values resonator frequency c1 c2 3.58mhz tbd tbd 1mhz tbd tbd 455khz tbd tbd note: c1 and c2 values are for guidance only. resonator recommended capacitor values external rc oscillator using the external system rc oscillator requires that a resistor, with a value between 24k and 1m , is con- nected between osc1 and vdd, and a capacitor is con- nected to ground. although this is a cost effective oscillator configuration, the oscillation frequency can vary with vdd, temperature and process variations and is therefore not suitable for applications where timing is critical or where accurate oscillator frequencies are re - quired. for the value of the external resistor r osc refer to the holtek website for typical rc oscillator vs. tem - perature and vdd characteristics graphics here only the osc1 pin is used, which is shared with i/o pin pa6, leaving pin pa5 free for use as a normal i/o pin. note that it is the only microcontroller internal circuitry to - gether with the external resistor, that determine the fre - quency of the oscillator. the external capacitor shown on the diagram does not influence the frequency of os - cillation.    2    -  c    
      
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HT46R92 rev. 1.10 40 november 5, 2008 external rtc oscillator when the microcontroller enters the power down mode, the system clock is switched off to stop microcontroller activity and to conserve power. however, in many microcontroller applications it may be necessary to keep some internal functions such as timers operational even when the microcontroller is in the power down mode. to do this, a 32768hz oscillator, also known as the real time clock or rtc oscillator, is provided. to implement this clock, the osc3 and osc4 pins should be con - nected to a 32768hz crystal. however, for some crys - tals, to ensure oscillation and accurate frequency generation, it may be necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crys- tal or resonator manufacturer
s specification. the exter- nal parallel feedback resistor, rp, is normally not required but in some cases may be needed to assist with oscillation start up. the mods bit in the mode reg- ister is used to select whether the external 32768hz os- cillator or the external crystal/external rc is used as the system oscillator. using the slower 32768hz oscilla - tor as the system oscillator will of course use less power and is known as the slow mode. internal ca, cb, rf typical values @ 5v, 25  c ca cb rf tbd tbd tbd rtc oscillator internal component values rtc oscillator c1 and c2 values crystal frequency c1 c2 cl 32768hz tbd tbd tbd note: 1. c1 and c2 values are for guidance only. 2. cl is the crystal manufacturer specified load capacitor value. 32768 hz crystal recommended capacitor values when the system enters the power down mode, the 32768hz oscillator will keep running and if it is selected as the timer and watchdog timer source clock, will also keep these functions operational. during power up there is a time delay associated with the rtc oscillator, waiting for it to start up. the qosc bit in the mode register, is provided to give a quick start-up function and can be used to minimise this delay. during a power up condition, this bit will be cleared to 0 which will initiate the rtc oscillator quick start-up func - tion. however, as there is additional power consumption associated with this quick start-up function, to reduce power consumption after start up takes place, it is rec - ommended that the application program should set the qosc bit high about 2 seconds after power on. it should be noted that, no matter what condition the qosc bit is set to, the rtc oscillator will always function normally, only there is more power consumption associated with the quick start-up function. watchdog timer oscillator the wdt oscillator is a fully self-contained free running on-chip rc oscillator with a typical period of 65  sat5v requiring no external components. when the device en- ters the power down mode, the system clock will stop running but the wdt oscillator continues to free-run and to keep the watchdog active. however, to preserve power in certain applications the wdt oscillator can be disabled via a configuration option.    ,    3  c    
      
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HT46R92 rev. 1.10 41 november 5, 2008 power down mode and wake-up power down mode all of the microcontrollers have the ability to enter a power down mode. when the device enters this mode, the normal operating current, will be reduced to an ex - tremely low standby current level. this occurs because when the device enters the power down mode, the sys - tem oscillator is stopped which reduces the power con - sumption to extremely low levels, however, as the device maintains its present internal condition, it can be woken up at a later stage and continue running, without requiring a full reset. this feature is extremely important in application areas where the mcu must have its power supply constantly maintained to keep the device in a known condition but where the power supply capacity is limited such as in battery applications. entering the power down mode there is only one way for the device to enter the power down mode and that is to execute the  halt  instruc - tion in the application program. when this instruction is executed, the following will occur:  the system oscillator will stop running and the appli - cation program will stop at the  halt  instruction.  the data memory contents and registers will maintain their present condition.  the wdt will be cleared and resume counting if the wdt clock source is selected to come from the wdt internal oscillator. the wdt will stop if its clock source originates from the system clock.  the i/o ports will maintain their present condition.  in the status register, the power down flag, pdf, will be set and the watchdog time-out flag, to, will be cleared. standby current considerations as the main reason for entering the power down mode is to keep the current consumption of the mcu to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. special atten - tion must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased cur - rent consumption. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the configuration options have en - abled the watchdog timer internal oscillator. wake-up after the system enters the power down mode, it can be woken up from one of various sources listed as follows:  an external reset  an external falling edge on port a  a system interrupt  a wdt overflow if the system is woken up by an external reset, the de - vice will experience a full system reset, however, if the device is woken up by a wdt overflow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the ac - tual source of the wake-up can be determined by exam - ining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the  halt  instruction. the to flag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other flags remain in their original status. each pin on port a can be setup via an individual config - uration option to permit a negative transition on the pin to wake-up the system. when a port a pin wake-up oc- curs, the program will resume execution at the instruc- tion following the  halt  instruction. if the system is woken up by an interrupt, then two possi- ble situations may occur. the first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume exe- cution at the instruction following the  halt  instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be ser - viced later when the related interrupt is finally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag is set to  1  be - fore entering the power down mode, the wake-up func - tion of the related interrupt will be disabled. no matter what the source of the wake-up event is, once a wake-up situation occurs, a time period equal to 1024 system clock periods will be required before normal sys - tem operation resumes. however, if the wake-up has originated due to an interrupt, the actual interrupt sub - routine execution will be delayed by an additional one or more cycles. if the wake-up results in the execution of the next instruction following the  halt  instruction, this will be executed immediately after the 1024 system clock period delay has ended.
HT46R92 rev. 1.10 42 november 5, 2008 watchdog timer the watchdog timer is provided to prevent program mal - functions or sequences from jumping to unknown loca - tions, due to certain uncontrollable external events such as electrical noise. it operates by providing a device reset when the wdt counter overflows. the wdt clock is sup - plied by one of three sources selected by configuration option: its own self contained dedicated internal wdt os - cillator, f sys /4 or the rtc oscillator. note that if the wdt configuration option has been disabled, then any instruc - tion relating to its operation will result in no operation. in the device, all watchdog timer options, such as en - able/disable, wdt clock source and clear instruction type all selected through configuration options. there are no internal registers associated with the wdt in the cost-effective a/d type mcu series. one of the wdt clock sources is an internal oscillator which has an ap - proximate period of 65  s at a supply voltage of 5v. how - ever, it should be noted that this specified internal clock period can vary with vdd, temperature and process variations. watchdog timer time-out value is of 2 14 /f s to 2 21 /f s . if the f sys /4 clock is used as the wdt clock source, it should be noted that when the system enters the power down mode, then the instruction clock is stopped and the wdt will lose its protecting purposes. for systems that operate in noisy environments, using the internal wdt oscillator is strongly recommended. under normal program operation, a wdt time-out will initialise a device reset and set the status bit to. how- ever, if the system is in the power down mode, when a wdt time-out occurs, the to bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the wdt. the first is an external hardware reset, which means a low level on the res pin, the second is using the watchdog software instruc - tions and the third is via a  halt  instruction. there are two methods of using software instructions to clear the watchdog timer, one of which must be chosen by configuration option. the first option is to use the sin - gle  clr wdt  instruction while the second is to use the two commands  clr wdt1  and  clr wdt2  . for the first option, a simple execution of  clr wdt  will clear the wdt while for the second option, both  clr wdt1  and  clr wdt2  must both be executed to successfully clear the wdt. note that for this second option, if  clr wdt1  is used to clear the wdt, successive executions of this instruction will have no effect, only the execution of a  clr wdt2  instruction will clear the wdt. similarly after the  clr wdt2  instruction has been executed, only a successive  clr wdt1  instruction can clear the watchdog timer. buzzer operating in a similar way to the programmable fre - quency divider, the buzzer function provides a means of producing a variable frequency output, suitable for ap - plications such as piezo-buzzer driving or other external circuits that require a precise frequency generator. the bz and bz pins form a complimentary pair, and are pin-shared with i/o pins, pa0 and pa1. a configuration option is used to select from one of three buzzer options. the first option is for both pins pa0 and pa1 to be used as normal i/os, the second option is for both pins to be configured as bz and bz buzzer pins, the third option selects only the pa0 pin to be used as a bz buzzer pin with the pa1 pin retaining its normal i/o pin function. note that the bz pin is the inverse of the bz pin which to - gether generate a differential output which can supply more power to connected interfaces such as buzzers. the buzzer is driven by the internal clock source, f s , which is then passed through a divider, the division ratio of which is selected by configuration options to provide a range of buzzer frequencies from f s /2 to f s /2 4 . the clock source that generates f s , which in turn controls the buzzer frequency, can originate from three different sources, the rtc oscillator, the wdt oscillator or the system oscillator/4, the choice of which is determined by the f s clock source configuration option. it is impor- tant to note that if the rtc oscillator is selected as the system clock, then f s and correspondingly the buzzer, will also have the rtc oscillator as its clock source. note that the buzzer frequency is controlled by configu - ration options, which select both the source clock for the internal clock f s and the internal division ratio. there are no internal registers associated with the buzzer fre - quency. if the configuration options have selected both pins pa0 and pa1 to function as a bz and bz complementary pair of buzzer outputs, then for correct buzzer operation it is essential that both pins must be setup as outputs by set - ting bits pac0 and pac1 of the pac port control register to zero. the pa0 data bit in the pa data register must also be set high to enable the buzzer outputs, if set low,  2 /   
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HT46R92 rev. 1.10 43 november 5, 2008 both pins pa0 and pa1 will remain low. in this way the single bit pa0 of the pa register can be used as an on/off control for both the bz and bz buzzer pin outputs. note that the pa1 data bit in the pa register has no control over the bz buzzer pin pa1. pa0/pa1 pin function control pac register pac0 pac register pac1 pa data register pa0 pa data register pa1 output function 001x pa0=bz pa1=bz 000x pa0=  0  pa1=  0  011x pa0=bz pa1=input line 010x pa0=  0  pa1=input line 10xd pa0=input line pa1=d 11xx pa0=input line pa1=input line note:  x  stands for don
t care  d  stands for data  0  or  1  if configuration options have selected that only the pa0 pin is to function as a bz buzzer pin, then the pa1 pin can be used as a normal i/o pin. for the pa0 pin to func- tion as a bz buzzer pin, pa0 must be setup as an output by setting bit pac0 of the pac port control register to zero. the pa0 data bit in the pa data register must also be set high to enable the buzzer output, if set low pin pa0 will remain low. in this way the pa0 bit can be used as an on/off control for the bz buzzer pin pa0. if the pac0 bit of the pac port control register is set high, then pin pa0 can still be used as an input even though the configuration option has configured it as a bz buzzer output. note that no matter what configuration option is chosen for the buzzer, if the port control register has setup the pin to function as an input, then this will override the con- figuration option selection and force the pin to always behave as an input pin. this arrangement enables the pin to be used as both a buzzer pin and as an input pin, so regardless of the configuration option chosen; the ac- tual function of the pin can be changed dynamically by the application program by programming the appropri- ate port control register bit. 
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buzzer output pin control note the above drawing shows the situation where both pins pa0 and pa1 are selected by configuration option to be bz and bz buzzer pin outputs. the port control register of both pins must have already been setup as out - put. the data setup on pin pa1 has no effect on the buzzer outputs.
HT46R92 rev. 1.10 44 november 5, 2008 configuration options configuration options refer to certain options within the mcu that are programmed into the device during the program - ming process. during the development process, these options are selected using the ht-ide software development tools. as these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later as the application software has no control over the configuration options. all options must be defined for proper system function, the details of which are shown in the table. no. options i/o options 1 pa0~pa7: wake-up enable or disable - bit option 2 pa pull-high enable or disable - by port oscillator option 3 system oscillator: crystal or rc pwm options 4 pa4~pa5: pwm0~pwm1 function selection 5 pwm mode: 6+2 or 7+1 mode selection timer options 6 timer/event counter clock sources: f sys /4 or f sp buzzer options 7 buzzer function: single bz enable, both bz and bz or both disable 8 buzzer frequency: f s /2, f s /4, f s /8, f s /16 time base options 9 time base time-out period: f s /2 5 ,f s /2 6 ,f s /2 7 ,f s /2 8 ,f s /2 9 ,f s /2 10 ,f s /2 11 ,f s /2 12 watchdog options 10 watchdog timer clock source: wdt oscillator, rtc oscillator or f sys /4 11 watchdog timer function: enable or disable 12 clrwdt instructions: 1 or 2 instructions lvr options 13 lvr function: enable or disable 14 lvr voltage: 2.1v, 3.15v or 4.2v lock options 15 lock all 16 partial lock
application circuits HT46R92 rev. 1.10 45 november 5, 2008    2    -        
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HT46R92 rev. 1.10 46 november 5, 2008 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5  s and branch or call instructions would be im - plemented within 1  s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be  clr pcl  or  mov pcl, a  . for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits.
HT46R92 rev. 1.10 47 november 5, 2008 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the  set [m].i  or  clr [m].i  instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the  halt  in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z
HT46R92 rev. 1.10 48 november 5, 2008 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the  clr wdt1  and  clr wdt2  instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both  clr wdt1  and  clr wdt2  instructions are consecutively executed. otherwise the to and pdf flags remain unchanged.
instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc  acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m]  acc+[m]+c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc  acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc  acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m]  acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc  acc  and  [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc  acc  and  x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m]  acc  and  [m] affected flag(s) z HT46R92 rev. 1.10 49 november 5, 2008
call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack  program counter + 1 program counter  addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m]  00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i  0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to  0 pdf  0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to  0 pdf  0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to  0 pdf  0 affected flag(s) to, pdf HT46R92 rev. 1.10 50 november 5, 2008
cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1
s complement). bits which previously containe d a 1 are changed to 0 and vice versa. operation [m]  [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1
s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc  [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m]  acc + 00h or [m]  acc + 06h or [m]  acc + 60h or [m]  acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m]  [m]  1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc  [m]  1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to  0 pdf  1 affected flag(s) to, pdf HT46R92 rev. 1.10 51 november 5, 2008
inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m]  [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc  [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter  addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc  [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc  x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m]  acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc  acc  or  [m] affected flag(s) z HT46R92 rev. 1.10 52 november 5, 2008
or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc  acc  or  x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m]  acc  or  [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter  stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter  stack acc  x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed be- fore returning to the main program. operation program counter  stack emi  1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1)  [m].i; (i = 0~6) [m].0  [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1)  [m].i; (i = 0~6) acc.0  [m].7 affected flag(s) none HT46R92 rev. 1.10 53 november 5, 2008
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1)  [m].i; (i = 0~6) [m].0  c c  [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1)  [m].i; (i = 0~6) acc.0  c c  [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i  [m].(i+1); (i = 0~6) [m].7  [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i  [m].(i+1); (i = 0~6) acc.7  [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i  [m].(i+1); (i = 0~6) [m].7  c c  [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i  [m].(i+1); (i = 0~6) acc.7  c c  [m].0 affected flag(s) c HT46R92 rev. 1.10 54 november 5, 2008
sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc  acc  [m]  c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m]  acc  [m]  c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m]  [m]  1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc  [m]  1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m]  ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i  1 affected flag(s) none HT46R92 rev. 1.10 55 november 5, 2008
siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m]  [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc  [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i  0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc  acc  [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m]  acc  [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc  acc  x affected flag(s) ov, z, ac, c HT46R92 rev. 1.10 56 november 5, 2008
swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0  [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0  [m].7 ~ [m].4 acc.7 ~ acc.4  [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc  [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m]  program code (low byte) tblh  program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m]  program code (low byte) tblh  program code (high byte) affected flag(s) none HT46R92 rev. 1.10 57 november 5, 2008
xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc  acc  xor  [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m]  acc  xor  [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc  acc  xor  x affected flag(s) z HT46R92 rev. 1.10 58 november 5, 2008
package information 44-pin qfp (10mm  10mm) outline dimensions symbol dimensions in mm min. nom. max. a13  13.4 b 9.9  10.1 c13  13.4 d 9.9  10.1 e  0.8  f  0.3  g 1.9  2.2 h  2.7 i 0.25  0.5 j 0.73  0.93 k 0.1  0.2 l  0.1   0  7  HT46R92 rev. 1.10 59 november 5, 2008 , 3 2 2 2 3 3 & ' - - 2 -  6 + 0  m g  , , - ,   
52-pin qfp (14mm  14mm) outline dimensions symbol dimensions in mm min. nom. max. a 17.3  17.5 b 13.9  14.1 c 17.3  17.5 d 13.9  14.1 e  1  f  0.4  g 2.5  3.1 h  3.4 i  0.1  j 0.73  1.03 k 0.1  0.2  0  7  HT46R92 rev. 1.10 60 november 5, 2008           
         
HT46R92 rev. 1.10 61 november 5, 2008 copyright  2008 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek
s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shanghai sales office) g room, 3 floor, no.1 building, no.2016 yi-shan road, minhang district, shanghai, china 201103 tel: 86-21-5422-4590 fax: 86-21-5422-4705 http://www.holtek.com.cn holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, gaoxin m 2nd, middle zone of high-tech industrial park, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor inc. (beijing sales office) suite 1721, jinyu tower, a129 west xuan wu men street, xicheng district, beijing, china 100031 tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 fax: 86-10-6641-0125 holtek semiconductor inc. (chengdu sales office) 709, building 3, champagne plaza, no.97 dongda street, chengdu, sichuan, china 610016 tel: 86-28-6653-6590 fax: 86-28-6653-6591 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com


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